Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's. FIG. 1 is a simplified schematic diagram of circuit 20 wherein ESD clamp 21 is placed between input/output (I/O) terminals 22 and ground or common terminal 23 of a SC device or IC to protect the other devices on the chip, that is, to protect circuit core 24 which is also coupled to I/O terminals 22 and common (e.g., “GND”) terminal 23. Zener diode symbol 21′ within ESD clamp 21 indicates that the function of ESD clamp 21 is to limit the voltage than can appear across circuit core 24 irrespective of the voltage applied to external terminals 22, 23. As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return.
FIG. 2 is a simplified schematic diagram illustrating internal components of prior art ESD clamp 31 which is inserted in circuit 20 in place of ESD clamp 21. ESD clamp 31 comprises bipolar transistor 25, having emitter 26, collector 27 and base 28, resistance 29 and Zener diode 30 having terminals 301, 302. Resistance 29 includes the inherent resistance of the base region of transistor 25 and any discrete resistance provided external to transistor 25. In some applications it is common to externally directly connect the base and emitter contacts in which case resistance 29 represents the inherent base resistance and any small contact resistance. The purpose of resistance 29 (and analogous resistances 29, 39, 39′ in FIGS. 4-7) is to keep the base and emitter at substantially the same potential unless there is an ESD event, so that in normal operation of circuit 20, ESD clamp 31 does not interfere with the operation of circuit core 24. When the voltage across terminals 22, 23 rises beyond a predetermined limit, Zener diode 30 turns on, thereby switching bipolar transistor 25 into conduction and desirably clamping the voltage across terminals 22, 23 at a level below a value capable of damaging circuit core 24. Design, construction and operation of such ESD devices is described for example in commonly owned U.S. Pat. No. 7,164,566 B2 “Electrostatic Discharge Protection Device and Method Therefore” by Hongzhong Xu et al, and further described by Danielle Coffing and Richard Ida in “Analysis of a Zener-Triggered Bipolar ESD Structure in a BiCMOS Technology”, IEEE BCTM 1998, pages 31-34, and by Joshi, Ida, Givelin and Rosenbaum in “An Analysis of Bipolar Breakdown and its Application to the Design of ESD Protection Circuits”, IEEE 01CH37167, 39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001, pages 240-245. FIG. 3 is an illustration of a typical current-voltage characteristic of an ESD clamp, where voltage Vt1 is referred to as the trigger voltage and voltage Vh is referred to as the holding voltage.